Exploring Abstract Interfaces in System-on-chip Integration a Dissertation Submitted to the Department of Electrical Engineering and the Committee on Graduate Studies of Stanford University in Partial Fulfillment of the Requirements for the Degree of Doctor of Philosophy

Modern mobile devices are marvels of computation. They can encode high­defnition video, processing and compressing over 350MB/s of image data in real time. They have no trouble driving displays with as much resolution as a full laptop, and smart­ phone manufacturers boast of running games with "console quality" graphics. Mobile devices pack all of this computational power into a 1­2\ hand­held package by inte­ grating a number of specialized hardware accelerators (IP) along with conventional CPU and GPUs in a system­on­chip (SoC). Unfortunately, creating these specialized systems is becoming increasingly expen­ sive. Since hardware accelerators come from a number of diferent sources and design cycles, diferent accelerator blocks will often contain incompatible hardware inter­ faces. Therefore, a large portion of SoC design cost comes in the form of designers manually interfacing each accelerator into a system. This work includes everything from building custom logic to wire up a block, to developing the drivers and API needed to take advantage of the hardware. My research focuses on generating these interfaces, including the physical hard­ ware used to tie IP blocks into a system and the associated software collateral. Lever­ aging recent trends such as High Level Synthesis and other hardware "generator" methodologies, I propose an IP interface abstraction and parameterization designed to describe the interface of most current IP blocks. By encoding this knowledge at a higher­level of abstraction, I am able to construct and demonstrate a hardware gen­ erator that maps an interface protocol description into synthesizable register transfer language (RTL), and that can automatically create hardware bridges between difer­ ent interconnect standards.